1. Field of the Invention
The present invention relates to a semiconductor device including a memory cell having a charge accumulation layer. For example, the invention relates to a configuration of a semiconductor device provided with a NAND type flash memory.
2. Description of the Related Art
Conventionally, an EEPROM (Electrically Erasable and Programmable Read Only Memory) is known as a nonvolatile semiconductor memory. Usually, the memory cell of an EEPROM has a MISFET structure including a stacked gate in which a charge accumulation layer and a control gate are stacked on a semiconductor substrate. Data is stored in the memory cell in a nonvolatile manner by a difference in threshold voltage between a state in which charges are injected in a charge accumulation layer and a state in which the charges are emitted.
In the NAND type EEPROM, electron injection into the charge accumulation layer (data write) and electron emission from the charge accumulation layer (data erase) are performed by a tunnel current which is passed through a tunnel insulation film provided between the charge accumulation layer and a semiconductor substrate. In a NOR type EEPROM, the electron emission from the charge accumulation layer is also performed by the tunnel current in order to be less affected by a short channel effect during the data erase.
The data erase is simultaneously performed on the plural memory cells in order to increase the number of memory cells erased per unit time. At this point a voltage not lower than 10V, for example, a positive voltage of 20V is applied to a well region where the memory cell is formed. On the other hand, during the data write, the well region is kept at 0V, and a voltage not lower than 10V is applied to a source and a drain. Therefore, the electric power necessary to charge and discharge the well region can be reduced to enhance the operation speed.
A charge pump circuit is used in an EEPROM in order to generate a high voltage not lower than 10V. For example, Jpn. Pat. Appln. KOKAI Publication Nos. 2001-231248, 2003-33008, 2003-51550, and 2003-102166 disclose charge pump circuits. Such charge pump circuits have a configuration in which plural rectifying elements are series-connected, and each rectifying element is formed by using an n-type MOS transistor in which a drain and a gate are connected.
In the charge pump circuit having the above-described configuration, a threshold voltage of a MOS transistor, which functions a certain rectifying element, is higher than that of a MOS transistor, which functions a preceding-stage rectifying element. As a result, in the series connection of the rectifying elements, boosting performance is lowered as the rectifying element is located in a later stage (as being closer to an output node). Therefore, in order to secure a sufficiently-boosted voltage, unfortunately, the number of stages of the rectifying element is increased, which enlarges the circuit area.